1. Field of the Invention
The present invention relates to ATM (Asynchronous Transfer Mode) data communication and, more particularly, to a cell buffer circuit for allowing ATM cells to be dealt with by an SDH (Synchronous Digital Hierarchy)-based interface.
2. Description of the Background Art
A conventional system for converting ATM cell data to SDH-based data includes a cell length converting and valid cell detecting section. This section removes an additional byte from input fifty-four byte ATM cell data and feed only the ATM cell data of valid cells to a FIFO (First-In First Out) memory. Such data are read out of the FIFO memory and mapped in the ATM cell area of an SDH frame generator. The data output from the SDH frame generator are converted to a serial signal and then output.
The problem with an SDH frame assigned to the SDH frame generator is that an overhead (OH) byte area makes the rate at which the cell data are read out of the FIFO memory lower than the rate at which they are written to the memory. As a result, when more than a preselected number of valid cells are continuously written to the FIFO memory, the memory overflows. To prevent the FIFO memory from overflowing, the memory delivers a back pressure signal to the cell length converting and valid cell detecting section when it is about to overflow, thereby inhibiting the above section from writing cell data in the memory. The back pressure signal, however, brings about another problem that it interrupts the delivery of valid cells from the cell length converting and valid cell detecting signal to the FIFO memory, causing valid cells to be lost.
It is therefore an object of the present invention to provide a cell buffer circuit capable of preventing valid cell data from being lost even when stopping the delivery of cell data to a FIFO memory in response to a back pressure signal.
In accordance with the present invention, a cell buffer circuit includes a cell data shifting section having a series connection of shift registers for sequentially shifting input cell data having a preselected length. The shift registers each delays the input cell data by an amount corresponding to the preselected length. A selector selects either the input cell data or cell data output from any one of the shift registers on a cell data basis. A controller controls the selector such that the selector stops, on receiving a back pressure signal when selecting the input cell data, delivery of cell data once and selects cell data output from the first shift register thereafter. The controller causes the selector to stop, on receiving the back pressure signal when selecting cell data output from the nth shift register, the delivery of cell data once and select cell data output from the n+1th shift register thereafter. Further, the controller causes the selector to stop, if the input cell data being selected by the selector are invalid, outputting the invalid cell data. In addition, the controller causes the selector to select, on receiving invalid input cell data when selecting the cell data output from the nth shift register, cell data output from the nxe2x88x921th shift register after the invalid input cell data have been transferred to the nth shift register.
Also, in accordance with the present invention, a cell buffer circuit includes a cell data shifting section having a shift register for shifting input cell data having a preselected length to thereby delay the input cell data by an amount corresponding to the preselected length. A selector selects either the input cell data or cell data output from the shift register on a cell data basis. A controller controls the selector such that the selector stops, on receiving a back pressure signal when selecting the input cell data, the delivery of cell data once and selects cell data output from the shift register thereafter, such that the selector stops, if the input cell data being selected by the selector are invalid, outputting the invalid cell data, and such that the selector selects, on receiving invalid input cell data when selecting the cell data output from the shift register, input cell data after the invalid input cell data have been transferred to the shift register.
Further, in accordance with the present invention, a cell buffer circuit includes a cell data shifting section having a series connection of shift registers for sequentially shifting input cell data having a preselected length. The shift registers each delays the input cell data by an amount corresponding to the preselected length. A selector control signal generator includes a counter whose initial count is xe2x80x9c0xe2x80x9d. The selector control signal generator increments, on receiving a back pressure signal, the count at the head of the next input cell data or decrements, if the count is n when invalid input cell data are input, the count at the head of the nth input cell data as counted from said invalid input cell data. In any case, the selector control signal generator outputs a selector control signal representative of the current count of the counter. A selector selects the input cell data when the selector control signal is representative of the count xe2x80x9c0xe2x80x9d or selects, when the selector control signal is representative of a count n, cell data output from the nth shift register. A write control signal generator generates a write control signal for inhibiting the writing of one cell of data output from the selector on receiving invalid input cell data when the count represented by the selector control signal is incremented or when the count is xe2x80x9c0xe2x80x9d.